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A Survey on Performance Optimization of Cache Memory in the Individual Nodes of Wireless Sensor Networks

Amulya V1 , Mohan K G2 , Ramesh Babu H. S3

Section:Survey Paper, Product Type: Journal Paper
Volume-07 , Issue-16 , Page no. 75-80, May-2019

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v7si16.7580

Online published on May 18, 2019

Copyright © Amulya V, Mohan K G, Ramesh Babu H. S . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Amulya V, Mohan K G, Ramesh Babu H. S, “A Survey on Performance Optimization of Cache Memory in the Individual Nodes of Wireless Sensor Networks,” International Journal of Computer Sciences and Engineering, Vol.07, Issue.16, pp.75-80, 2019.

MLA Style Citation: Amulya V, Mohan K G, Ramesh Babu H. S "A Survey on Performance Optimization of Cache Memory in the Individual Nodes of Wireless Sensor Networks." International Journal of Computer Sciences and Engineering 07.16 (2019): 75-80.

APA Style Citation: Amulya V, Mohan K G, Ramesh Babu H. S, (2019). A Survey on Performance Optimization of Cache Memory in the Individual Nodes of Wireless Sensor Networks. International Journal of Computer Sciences and Engineering, 07(16), 75-80.

BibTex Style Citation:
@article{V_2019,
author = {Amulya V, Mohan K G, Ramesh Babu H. S},
title = {A Survey on Performance Optimization of Cache Memory in the Individual Nodes of Wireless Sensor Networks},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {5 2019},
volume = {07},
Issue = {16},
month = {5},
year = {2019},
issn = {2347-2693},
pages = {75-80},
url = {https://www.ijcseonline.org/full_spl_paper_view.php?paper_id=1282},
doi = {https://doi.org/10.26438/ijcse/v7i16.7580}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v7i16.7580}
UR - https://www.ijcseonline.org/full_spl_paper_view.php?paper_id=1282
TI - A Survey on Performance Optimization of Cache Memory in the Individual Nodes of Wireless Sensor Networks
T2 - International Journal of Computer Sciences and Engineering
AU - Amulya V, Mohan K G, Ramesh Babu H. S
PY - 2019
DA - 2019/05/18
PB - IJCSE, Indore, INDIA
SP - 75-80
IS - 16
VL - 07
SN - 2347-2693
ER -

           

Abstract

The wireless networks are constrained networks with limited battery backup and memory. The nodes in the Wireless Sensor Network use memory buffers to keep track of the sequence number of the Transport layer segments. This helps to resend the packets during the time of packet loss. The fast retransmission of the lost packets is done by nodes of Wireless Sensor Network with the help of fastest form of memory called as cache memory. This helps to achieve reliability. Understanding the working of cache memory in fulfilling such a great responsibility is a challenge. The survey has been conducted to understand the different types of processors and memories that could be used in the nodes of wireless sensor networks. An overview of optimization methods on cache memory and cache mapping mechanisms to improve the performance of the cache are also studied.

Key-Words / Index Term

Wireless Sensor Networks (WSN), Cache memory, performance optimization, survey

References

[1] Waltenegus Dargie and Christian Poellabauer, “Fundamentals of Wireless sensor theory and practice”
[2] Safaa S. Omran and Ibrahim A. Amory, “Design of Two-Dimensional Reconfigurable Cache memory using FPGA”, IEEE 10.1109/ICEDSA.2016.7818502, 2016,
[3] Santana Gil, A. D. Benavides Benitez, J.I., Hernandez Calviño, M. , Herruzo Gómez, E , “Reconfigurable Cache implemented on an FPGA”, International Conference on Reconfigurable Computing, IEEE 10.1109/ReConFig.2010.26, 2010
[4] Dinesh Kumar Gupta, “A Review on Wireless Sensor Networks”, Inter-national Conference on Recent Trends in Applied Sciences with Engineering Applications, ISSN 2224- 610X, Vol.3, No.1, IEEE 10.1109/ICAL.2012.6308240, 2013
[5] Melchizedek I. Alipio and Nestor Michael C. Tiglao,” Analysis of Cache-based Transport Protocol at Congestion in Wireless Sensor Networks”, International Conference on Information Networking (ICOIN), IEEE, 10.1109/ICOIN.2017.7899459, 2017
[6] Bruno Marchil, Antonio Grilo, Mario Nunes, “DTSN: Distributed Transport for Sensor Networks”, 12th IEEE Symposium on Computers and Communications, IEEE, 1-4244-1521-7/0, 2007
[7] Adam Dunkels, Juan Alonso, Thiemo Voigt, “Distributed TCP caching for wireless sensor networks”, SICS Technical Report T2004:06 ISSN 1100-3154 ISRN: SICS-T–2004/06- SE, 2004.
[8] Atif Sharif, Vidyasagar M. Potdar, A. J. D Rathnayaka, “ERCTP: End-to-end Reliable and Congestion aware Transport layer Protocol for heterogeneous WSN”, Scalable Computing: Practice and Experience, vol. 11, no. 4, 2010.
[9] Ahmed Ayadi, Patrick Maill´e, and David,” Improving Distributed TCP Caching for Wireless Sensor Networks”, The 9th IFIP Annual Mediterranean AdHoc Networking Workshop (Med-Hoc-Net), IEEE 10.1109/MEDHOCNET.2010.5546858, 2010.
[10] Su Liu1, Yan Tang*, Yonghua Liu2, “A survey of transport protocol for wireless sensor networks”, 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet), IEEE 10.1109/CECNet.2012.6202037, 2012
[11] Fred Stann, John Heidemann, “RMST: reliable data transport in sensor networks”, Proceedings of the First IEEE International Workshop on Sensor Network Protocols and Applications, IEEE 10.1109/SNPA.2003.1203361, 2003
[12] Chieh-Yih Wan, Andrew T. Campbell, Member, IEEE, and Lakshman Krishnamurthy, “Pump-slowly, fetch quickly (PSFQ): a reliable transport protocol for sensor networks”, IEEE Journal on Selected Areas in Communications, vol. 23, no. 4, IEEE 10.1109/JSAC.2005.843554 , 2005
[13] Yuhua Liu and Hao Huang, “Multi-path-based Distributed TCP Caching for Wireless Sensor Networks”, Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD), IEEE 10.1109/SNPD.2007.297, 2007
[14] Noel Eisley, Li-ShiuanPeh, and _Li Shang, “ In- Network Cache Coherence”, IEEE Computer Architecture Letters , Vol. 5, IEEE Computer Architecture Letters, 2006
[15] Wei Ye, John Heidemann, Deborah Estrin , “An Energy-Efficient MAC Protocol for Wireless Sensor Networks”, Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies, IEEE 10.1109/INFCOM.2002.1019408, 2002
[16] Markus Kowarschik and Christian Wei, “An Overview of Cache Optimization Techniquesand Cache Aware Numerical Algorithms”, Deutsche Forschungsgemeinschaft (German Science Foundation), projects Ru 422/7-1,2,3.
[17] J.L. Hennessy and D.A. Patterson, “Computer Architecture: A Quantitative Approach” Morgan Kaufmann Publisher, Inc., San Francisco, California, USA, second edition, 1996.
[18] M.S. Lam, E.E. Rothberg, and M.E. Wolf, “The Cache Performance and Optimizations of Blocked Algorithms” In Proc. of the Fourth Int. Conference on Architectural Support for Programming Languages and Operating Systems, pp 63-74,Palo Alto, California, USA, 1991.
[19] J. Torrellas, M. Lam, and J. Hennessy, “Shared Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates”, In Proc. of the Int. Conference on Parallel Processing, volume 2, pp 266-270, Pennsylvania, USA, 1990.
[20] G. Rivera and C.-W. Tseng, “Data Transformations for Eliminating Conflict Misses” In Proc. of the ACM SIGPLAN Conference on Programming Language Design and Implementation, Montreal, Canada, 1998.
[21] T. Jeremiassen and S. Eggers, “Reducing False Sharing on Shared Memory Multiprocessors through Compile Time Data Transformations” In Proc. of the Fifth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp 179-188, Santa Barbara, California, USA, 1995.
[22] R. Allen and K. Kennedy, “Optimizing Compilers for Modern Architectures” Morgan Kaufmann Publishers, San Francisco, California, USA, 2001.
[23] Y. Song and Z. Li, “New Tiling Techniques to Improve Cache Temporal Locality”, In Proc. of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp 215-228, Atlanta, Georgia, USA, 1999.
[24] M.E. Wolf and M.S. Lam “A Data Locality Optimizing Algorithm” In Proc. of theSIGPLAN`91 Symposium on Programming Language Design and Implementation, volume 26 of SIGPLAN Notices, pp 33-44, Toronto, Canada, 1991.