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A Comparative Study of Full Adder Using Different Logic Style

Eshita Sarkar1 , Santasri Giri Tunga2 , Annesa Samanta3

Section:Review Paper, Product Type: Journal Paper
Volume-04 , Issue-06 , Page no. 22-25, Aug-2016

Online published on Sep 03, 2016

Copyright © Eshita Sarkar, Santasri Giri Tunga, Annesa Samanta . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Eshita Sarkar, Santasri Giri Tunga, Annesa Samanta, “A Comparative Study of Full Adder Using Different Logic Style,” International Journal of Computer Sciences and Engineering, Vol.04, Issue.06, pp.22-25, 2016.

MLA Style Citation: Eshita Sarkar, Santasri Giri Tunga, Annesa Samanta "A Comparative Study of Full Adder Using Different Logic Style." International Journal of Computer Sciences and Engineering 04.06 (2016): 22-25.

APA Style Citation: Eshita Sarkar, Santasri Giri Tunga, Annesa Samanta, (2016). A Comparative Study of Full Adder Using Different Logic Style. International Journal of Computer Sciences and Engineering, 04(06), 22-25.

BibTex Style Citation:
@article{Sarkar_2016,
author = {Eshita Sarkar, Santasri Giri Tunga, Annesa Samanta},
title = {A Comparative Study of Full Adder Using Different Logic Style},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {8 2016},
volume = {04},
Issue = {06},
month = {8},
year = {2016},
issn = {2347-2693},
pages = {22-25},
url = {https://www.ijcseonline.org/full_spl_paper_view.php?paper_id=115},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_spl_paper_view.php?paper_id=115
TI - A Comparative Study of Full Adder Using Different Logic Style
T2 - International Journal of Computer Sciences and Engineering
AU - Eshita Sarkar, Santasri Giri Tunga, Annesa Samanta
PY - 2016
DA - 2016/09/03
PB - IJCSE, Indore, INDIA
SP - 22-25
IS - 06
VL - 04
SN - 2347-2693
ER -

           

Abstract

In recent year, power dissipation is one of the biggest challenges in VLSI design. Adder circuits are the main sources of power dissipation in signal processing units. By reducing the number of transistors in the circuits and the design structures are may occupied small area and low power design. In this paper a Full Adder Circuit is designed by using CMOS, Transmission gates and pass Transistor logic and the power and delay are analysed. Power consumption and speed are two important but conflicting design aspects; hence a better way to evaluate circuit performance is power delay product (PDP). The designs are implemented and power, delay results are obtained by using TANNER EDA Tool. The results show that the transistor counts, delay and the power required are significantly concentrated in the design.

Key-Words / Index Term

Full Adder, CMOS, Transmission Gate (TG), Pass Transistor, Power Dissipation, Delay, PDP

References

[1] Sung-Mo Kang and Yusuf Leblebici; “CMOS digital integrated circuits: analysis and design”; Tata Mcgraw-Hill, Third Edition, 2003
[2] Kaushik Roy and S.C.Prasad, “Low power CMOS VLSI circuit design”, Wiley, 2000.
[3] Debika Chaudhuri, Atanu Nag, Sukanta Bose; “Low Power Full Adder Circuit Implemented In Different Logic”; IJIRSET, Volume3, Special Issue 6, February 2014
[4] D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” IEEE Proc. Circuits Devices Syst., vol. 148, no. 1, pp. 19–24, Feb. 2001.
[5] Vahid Foroutan and Keivan Navi, “Low Power Dynamic CMOS Full-Adder Cell”; IJCSIT, Vol.6(3), 2015
[6] Nishan Singh, Mandeep Kaur, Amardeep singh, Puneet Jain, “An Efficient Full Adder Design using Different Logic Styles”; IJCA, Volume 98 – No.21, July 2014