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Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology

Punith Kumar M B1 , Sreekantesha H N2

Section:Research Paper, Product Type: Journal Paper
Volume-07 , Issue-14 , Page no. 7-11, May-2019

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v7si14.711

Online published on May 15, 2019

Copyright © Punith Kumar M B, Sreekantesha H N . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Punith Kumar M B, Sreekantesha H N, “Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology,” International Journal of Computer Sciences and Engineering, Vol.07, Issue.14, pp.7-11, 2019.

MLA Style Citation: Punith Kumar M B, Sreekantesha H N "Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology." International Journal of Computer Sciences and Engineering 07.14 (2019): 7-11.

APA Style Citation: Punith Kumar M B, Sreekantesha H N, (2019). Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology. International Journal of Computer Sciences and Engineering, 07(14), 7-11.

BibTex Style Citation:
@article{B_2019,
author = {Punith Kumar M B, Sreekantesha H N},
title = {Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {5 2019},
volume = {07},
Issue = {14},
month = {5},
year = {2019},
issn = {2347-2693},
pages = {7-11},
url = {https://www.ijcseonline.org/full_spl_paper_view.php?paper_id=1079},
doi = {https://doi.org/10.26438/ijcse/v7i14.711}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v7i14.711}
UR - https://www.ijcseonline.org/full_spl_paper_view.php?paper_id=1079
TI - Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology
T2 - International Journal of Computer Sciences and Engineering
AU - Punith Kumar M B, Sreekantesha H N
PY - 2019
DA - 2019/05/15
PB - IJCSE, Indore, INDIA
SP - 7-11
IS - 14
VL - 07
SN - 2347-2693
ER -

           

Abstract

In today’s world, number of communication protocols for both long and short distance communication purpose, long distance protocols is USB (Universal Serial Bus), ETHERNET, PCI-EXPRESS. SPI (Serial Peripheral interface) and I2C are used for short distance communication protocols. SPI is one of the commonly used bus protocol for connecting peripheral devices to microprocessor .SPI is full duplex, high speed an synchronous bus protocol used for on-board or intra-chip communication In this project the configurable architecture of SPI Protocol with Wishbone Interface has been designed .The main advantage of this design is it overcomes the weaknesses of traditional SPI Bus protocol. As the complexity of the circuit is numerous so there is need of verification methodology to quench the product failure. This project emphasizes on verification of SPI master core verification using Universal Verification Methodology.

Key-Words / Index Term

SPI, Wishbone, UVM, SystemVerilog

References

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