Open Access   Article Go Back

A Novel Low Power Full Adder Using a Modified Domino Logic

Somayyeh Jafarali Jassbi1 , 2 , Moloud Mousavi3

Section:Research Paper, Product Type: Journal Paper
Volume-4 , Issue-6 , Page no. 8-11, Jun-2016

Online published on Jul 01, 2016

Copyright © Somayyeh Jafarali Jassbi, , Moloud Mousavi . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

View this paper at   Google Scholar | DPI Digital Library

XML View
PDF Download

How to Cite this Paper

  • IEEE Citation
  • MLA Citation
  • APA Citation
  • BibTex Citation
  • RIS Citation

IEEE Style Citation: Somayyeh Jafarali Jassbi, , Moloud Mousavi, “A Novel Low Power Full Adder Using a Modified Domino Logic,” International Journal of Computer Sciences and Engineering, Vol.4, Issue.6, pp.8-11, 2016.

MLA Style Citation: Somayyeh Jafarali Jassbi, , Moloud Mousavi "A Novel Low Power Full Adder Using a Modified Domino Logic." International Journal of Computer Sciences and Engineering 4.6 (2016): 8-11.

APA Style Citation: Somayyeh Jafarali Jassbi, , Moloud Mousavi, (2016). A Novel Low Power Full Adder Using a Modified Domino Logic. International Journal of Computer Sciences and Engineering, 4(6), 8-11.

BibTex Style Citation:
@article{Jassbi_2016,
author = {Somayyeh Jafarali Jassbi, , Moloud Mousavi},
title = {A Novel Low Power Full Adder Using a Modified Domino Logic},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {6 2016},
volume = {4},
Issue = {6},
month = {6},
year = {2016},
issn = {2347-2693},
pages = {8-11},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=957},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=957
TI - A Novel Low Power Full Adder Using a Modified Domino Logic
T2 - International Journal of Computer Sciences and Engineering
AU - Somayyeh Jafarali Jassbi, , Moloud Mousavi
PY - 2016
DA - 2016/07/01
PB - IJCSE, Indore, INDIA
SP - 8-11
IS - 6
VL - 4
SN - 2347-2693
ER -

VIEWS PDF XML
1715 1632 downloads 1483 downloads
  
  
           

Abstract

A low power and high speed Full adder circuit design using a new CMOS domino logic family is presented in this paper. The presented domino logic is based on Magnetic Tunnel Junction Elements (MTJ) in Gate Diffusion Input (GDI) Technique. Compared to static CMOS logic circuits, dynamic logic circuits are important as it provides better speed and has less transistor requirement. The proposed circuit has very low dynamic power consumption and less delay compared to the recently proposed circuit techniques for the dynamic logic styles. Moreover, it will be shown that the proposed circuit is extremely fault tolerant. The monte carlo simulation is performed to emphasis the fault tolerance of proposed full adder. The proposed full adder is simulated using standard 0.18 um CMOS technology.

Key-Words / Index Term

Domino, Full Adder, Buffer, Low Power

References

[I] G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, pp. 114 -117,1965.1. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp. 68-73.
[2] R. R. Schaller, "Moore's law: Past, present and future," IEEE Spectrum, vol. 34, no. 6, pp. 52-59, Jun. 1997.
[3] B. Doyle, R. Arghavani, D. Barlage, S. Datta, M. Doczy, 1. Kavalieros, A. Murthy, and R. Chau, "Transistor elements for 30 nm physical gate lengths and beyond," Intel Technol. 1., vol. 6, no. 2, pp. 42-54, May 2002.
[4] S. Sugahara and 1. Nitta, "Spin-transistor electronics: an overview and outlook," Proc. IEEE, vol. 98, pp. 2124-2154, Dec. 2010. [5] V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi, "Analysis of high performance fast feedthrough logic families in CMOS", IEEE Trans. Cir. & syst. II, vol. 54, no. 6, Jun. 2007, 489- 493.
[5] Dhruva Kumari, Monisha SaW, Aminul Islam, “Design of 2: 1 Multiplexer and 1:2 Demultiplexer Using Magnetic Tunnel Junction Elements,” IEEE, 2013.
[6] M. Hosoml, H. Yamaglshl, T. Yamamoto, K. Bessho, Y. HlgO, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, H. Nagao, and H. Kano, "A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram," IEEE International Electron Devices Meeting, IEDM Technical Digest, pp. 459-462, Dec. 2005.
[7] W. Zhao, E. Belhaire, C. Chappert, and P. Mazoyer, "Spintronic device based non-volatile low standby power sram," IEEE Computer Society Annual Symposium on VLSI, pp. 40-45, April 2008.
[8] H. Meng, 1. Wang, and 1. P. Wang, "A spintronics full adder for magnetic CPU," IEEE Electron. Devices Lett., vol. 26, no. 6, pp. 360-362, Jun. 2005.
[9] S. Patil, X. Yao, H. Meng, 1.-P. Wang, and D. Lilja,"Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions," Proceedings ofthe 5th conference on Computing frontiers, pp. 171-178, 2008.
[10] W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, and B. Dieny, "A non­volatile flip-flop in magnetic fpga chip," International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTTS), pp. 323-326,2006.
[11] S. Lee, N. Kim, H. Yang, G. Lee, S. Lee, and H. Shin, "The 3- bit gray counter based on magnetic-tunnel-junction elements," IEEE Transactions on Magnetics, vol. 43, no. 6, pp. 2677-2679, June 2007.
[12] S. Patil, A. Lyle, J. Harms, D. Lilja and 1.-P. Wang, "Spintronic logic gates for spintronic data using magnetic tunnel junctions," in Proc. IEEE Int. Conf. Computer Design, 2010, pp. 125-131, Oct. 2010.
[13] 1. Wang, H. Meng, and 1. P. Wang, "Programmable spintronics logic device based on a magnetic tunnel junction element," J. Appl. Phys., vol. 97, no. 10, p. 10D 509, May 2005.
[14] A. Ney, C. Pampuch, R. Koch, and K. H. Ploog, "Programmable computing with a single magnetoresistive element," Nature, vol. 425, pp. 485-487, Oct. 2003.
[15] N. Srinivasa Gupta, M. Satyanarayana, “A Novel Domino Logic for Arithmetic Circuits” International Journal of Innovative Technology and Exploring Engineering, Volume-3, Issue-3, August 2013.
[16] C.-K. Tung, S.-H. Shieh and C.-H. Cheng, “Low-power high-speed full adder for portable electronic applications” ELECTRONICS LETTERS, Vol. 49, No. 17, 2013.
[17] Yi WEI, Ji-zhong SHEN, “Design of a novel low power 8-transistor 1-bit full adder cell” Journal of Zhejiang University-SCIENCE , 2011.