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Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies

L.S. Bandaru1 , V.K. Sandepudi2 , C. Sindhuja3

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-2 , Page no. 6-10, Feb-2014

Online published on Feb 28, 2014

Copyright © L.S. Bandaru, V.K. Sandepudi, C. Sindhuja . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: L.S. Bandaru, V.K. Sandepudi, C. Sindhuja, “Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.2, pp.6-10, 2014.

MLA Style Citation: L.S. Bandaru, V.K. Sandepudi, C. Sindhuja "Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies." International Journal of Computer Sciences and Engineering 2.2 (2014): 6-10.

APA Style Citation: L.S. Bandaru, V.K. Sandepudi, C. Sindhuja, (2014). Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies. International Journal of Computer Sciences and Engineering, 2(2), 6-10.

BibTex Style Citation:
@article{Bandaru_2014,
author = {L.S. Bandaru, V.K. Sandepudi, C. Sindhuja},
title = {Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {2 2014},
volume = {2},
Issue = {2},
month = {2},
year = {2014},
issn = {2347-2693},
pages = {6-10},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=42},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=42
TI - Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies
T2 - International Journal of Computer Sciences and Engineering
AU - L.S. Bandaru, V.K. Sandepudi, C. Sindhuja
PY - 2014
DA - 2014/02/28
PB - IJCSE, Indore, INDIA
SP - 6-10
IS - 2
VL - 2
SN - 2347-2693
ER -

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Abstract

The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the five port router for network on chip using the latest verification methodologies, Hardware Verification Languages(s) and EDA tools and qualifies the Design for Synthesis and implementation. This Router design contains Four output ports and one input port, it is packet based Protocol. This Design consists of Registers, FSM and FIFO�s. The Verification goes on it finds functional coverage of the Network Router by using System Verilog.

Key-Words / Index Term

Systemverilog, Ficinalcoverage, Assertions, Randomizations, FIFO, FSM, Netwokonchip, Verification Methodologies, Registerblock

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