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An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier

T. Kavitha1 , B. Karunaiah2

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-10 , Page no. 30-32, Oct-2014

Online published on Nov 02, 2014

Copyright © T. Kavitha , B. Karunaiah . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: T. Kavitha , B. Karunaiah , “An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.10, pp.30-32, 2014.

MLA Style Citation: T. Kavitha , B. Karunaiah "An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier." International Journal of Computer Sciences and Engineering 2.10 (2014): 30-32.

APA Style Citation: T. Kavitha , B. Karunaiah , (2014). An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier. International Journal of Computer Sciences and Engineering, 2(10), 30-32.

BibTex Style Citation:
@article{Kavitha_2014,
author = {T. Kavitha , B. Karunaiah },
title = {An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {10 2014},
volume = {2},
Issue = {10},
month = {10},
year = {2014},
issn = {2347-2693},
pages = {30-32},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=279},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=279
TI - An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier
T2 - International Journal of Computer Sciences and Engineering
AU - T. Kavitha , B. Karunaiah
PY - 2014
DA - 2014/11/02
PB - IJCSE, Indore, INDIA
SP - 30-32
IS - 10
VL - 2
SN - 2347-2693
ER -

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Abstract

Multiplication may be a for the most part used mathematical process, considerably in signal process and scientific applications. Multiplication having hardware challenge, and therefore the main criterion of upper speed, lower cost, and fewer VLSI space, the most apprehension in customary multiplication, typically realized by K no of cycles with shifting and adding, is to hurry up the underlying multi-operand addition of partial merchandise. during this paper we have a tendency to studied the changed Booth encryption (MBE) technique that has been introduced to scale back the quantity of PP rows, still keeping each straightforward and quick enough the generation method of every row.

Key-Words / Index Term

Modified Booth Encoding, higher speed, lower cost, and less VLSI area

References

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[2] C.H. Bennett, “Logical Reversibility of Computation”, IBM J.Research and Development, pp. 525-532, November 1973.
[3] T. Toffoli., “Reversible Computing”, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).
[4] E. Fredkin and T. Toffoli, “Conservative logic,” Int’l J. Theoretical Physics, Vol. 21, pp.219–253, 1982.

[5] R. Feynman, “Quantum Mechanical Computers,” Optics News, Vol.11, pp. 11–20, 1985.
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[7] A. Peres, “Reversible Logic and Quantum Computers”, Physical review A, 32:3266- 3276, 1985.
[8] W. N. N. Hung, X. Song, G. Yang, J. Yang and M. Perkowski, “Quantum Logic Synthesis by Symbolic Reachability Analysis”, Proc. 41st annual .