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Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach

P. Gopi Krishna1 , Dr.K.V.Subrahmanyam 2 , S Chandra Sekhar3

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-10 , Page no. 19-25, Oct-2014

Online published on Nov 02, 2014

Copyright © P. Gopi Krishna, Dr.K.V.Subrahmanyam , S Chandra Sekhar . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: P. Gopi Krishna, Dr.K.V.Subrahmanyam , S Chandra Sekhar, “Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.10, pp.19-25, 2014.

MLA Style Citation: P. Gopi Krishna, Dr.K.V.Subrahmanyam , S Chandra Sekhar "Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach." International Journal of Computer Sciences and Engineering 2.10 (2014): 19-25.

APA Style Citation: P. Gopi Krishna, Dr.K.V.Subrahmanyam , S Chandra Sekhar, (2014). Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach. International Journal of Computer Sciences and Engineering, 2(10), 19-25.

BibTex Style Citation:
@article{Krishna_2014,
author = {P. Gopi Krishna, Dr.K.V.Subrahmanyam , S Chandra Sekhar},
title = {Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {10 2014},
volume = {2},
Issue = {10},
month = {10},
year = {2014},
issn = {2347-2693},
pages = {19-25},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=277},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=277
TI - Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach
T2 - International Journal of Computer Sciences and Engineering
AU - P. Gopi Krishna, Dr.K.V.Subrahmanyam , S Chandra Sekhar
PY - 2014
DA - 2014/11/02
PB - IJCSE, Indore, INDIA
SP - 19-25
IS - 10
VL - 2
SN - 2347-2693
ER -

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Abstract

Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, optical information processing, quantum computing and nanotechnology. This research proposes a new implementation of adder in reversible logic. The design reduces the number of gate operations compared to the existing adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay. We can use it to construct more complex systems in nanotechnology.

Key-Words / Index Term

Adder, Decimal Arithmetic, Reversible logic, Garbage output, HNG gate

References

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