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Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits

B. Balaji1 , S.S. Malik2

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-9 , Page no. 75-77, Sep-2014

Online published on Oct 04, 2014

Copyright © B. Balaji, S.S. Malik . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: B. Balaji, S.S. Malik, “Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.9, pp.75-77, 2014.

MLA Style Citation: B. Balaji, S.S. Malik "Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits." International Journal of Computer Sciences and Engineering 2.9 (2014): 75-77.

APA Style Citation: B. Balaji, S.S. Malik, (2014). Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits. International Journal of Computer Sciences and Engineering, 2(9), 75-77.

BibTex Style Citation:
@article{Balaji_2014,
author = {B. Balaji, S.S. Malik},
title = {Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {9 2014},
volume = {2},
Issue = {9},
month = {9},
year = {2014},
issn = {2347-2693},
pages = {75-77},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=257},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=257
TI - Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits
T2 - International Journal of Computer Sciences and Engineering
AU - B. Balaji, S.S. Malik
PY - 2014
DA - 2014/10/04
PB - IJCSE, Indore, INDIA
SP - 75-77
IS - 9
VL - 2
SN - 2347-2693
ER -

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Abstract

In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel embeddedlogic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs.

Key-Words / Index Term

Flip-Flops, High-Speed, Leakage Power, Low-Power.

References

[1] J. Yuan and C. Svensson, �New single-clock CMOS latches and flipflops with improved speed and power savings,�IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 62�69, Jan. 1997.
[2] A. Hirata, K. Nakanishi, M. Nozoe, and A. Miyoshi, �The cross chargecontrol flip-flop: A low-power and high-speed flip-flop suitable for mobile application SoCs,� inProc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 306�307.
[3] N. Nedovic, M. Aleksic, and V. G. Oklobdzija, �Conditional pre-charge techniques for power-efficient dual-edge clocking,� inProc. Int. Symp. Low-Power Electron. Design, 2002, pp. 56�59.
[4] P. Zhao, T. K. Darwish, and M. A. Bayoumi, �High-performance and low-power conditional discharge flip-flop,� IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477�484, May 2004.
[5] V. Stojanovic and V. Oklobdzija, �Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems,� IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536�548, Apr. 1999
[6] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: PrenticeHall, 2003.