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Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL

D.V. Gopal1 , M.M. Reddy2

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-5 , Page no. 29-31, May-2014

Online published on May 31, 2014

Copyright © D.V. Gopal, M.M. Reddy . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: D.V. Gopal, M.M. Reddy, “Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.5, pp.29-31, 2014.

MLA Style Citation: D.V. Gopal, M.M. Reddy "Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL." International Journal of Computer Sciences and Engineering 2.5 (2014): 29-31.

APA Style Citation: D.V. Gopal, M.M. Reddy, (2014). Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL. International Journal of Computer Sciences and Engineering, 2(5), 29-31.

BibTex Style Citation:
@article{Gopal_2014,
author = {D.V. Gopal, M.M. Reddy},
title = {Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {5 2014},
volume = {2},
Issue = {5},
month = {5},
year = {2014},
issn = {2347-2693},
pages = {29-31},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=154},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=154
TI - Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL
T2 - International Journal of Computer Sciences and Engineering
AU - D.V. Gopal, M.M. Reddy
PY - 2014
DA - 2014/05/31
PB - IJCSE, Indore, INDIA
SP - 29-31
IS - 5
VL - 2
SN - 2347-2693
ER -

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Abstract

This project deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit unsigned integer multiplier. Both the VLSI design of multiplier multiplies two 32-bit unsigned integer values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation whereas in CSLA based multiplier also uses nearly the same delay time for multiplication operation the overall simulation can be observed by using model sim and the synthesis report can be given by using Xilinx ise.

Key-Words / Index Term

CLAA; CSLA; Delay; Area; Array Multiplier; HDL Modeling & Simulation

References

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