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Comparative Study and Performance Analysis of Cache Coherence Protocols

S. Kumar1 , K. Gupta2

  1. Dept. of Computer Science and Engineering, Rajkiya Engineering College, Kannauj, India.
  2. Dept. of Computer Science, GLS University, Ahmedabad, India.

Correspondence should be addressed to: swadheshkumar@gmail.com.

Section:Research Paper, Product Type: Journal Paper
Volume-5 , Issue-5 , Page no. 213-216, May-2017

Online published on May 30, 2017

Copyright © S. Kumar, K. Gupta . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: S. Kumar, K. Gupta, “Comparative Study and Performance Analysis of Cache Coherence Protocols,” International Journal of Computer Sciences and Engineering, Vol.5, Issue.5, pp.213-216, 2017.

MLA Style Citation: S. Kumar, K. Gupta "Comparative Study and Performance Analysis of Cache Coherence Protocols." International Journal of Computer Sciences and Engineering 5.5 (2017): 213-216.

APA Style Citation: S. Kumar, K. Gupta, (2017). Comparative Study and Performance Analysis of Cache Coherence Protocols. International Journal of Computer Sciences and Engineering, 5(5), 213-216.

BibTex Style Citation:
@article{Kumar_2017,
author = {S. Kumar, K. Gupta},
title = {Comparative Study and Performance Analysis of Cache Coherence Protocols},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {5 2017},
volume = {5},
Issue = {5},
month = {5},
year = {2017},
issn = {2347-2693},
pages = {213-216},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=1292},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=1292
TI - Comparative Study and Performance Analysis of Cache Coherence Protocols
T2 - International Journal of Computer Sciences and Engineering
AU - S. Kumar, K. Gupta
PY - 2017
DA - 2017/05/30
PB - IJCSE, Indore, INDIA
SP - 213-216
IS - 5
VL - 5
SN - 2347-2693
ER -

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Abstract

Cache memory is a small less access time semiconductor memory that sits between the processor and memory in the memory hierarchy to bridge the speed mismatch between processor and main memory. Multiprocessor System contains multiple processors working simultaneously and share memory. Multiprocessors are most widely used in computational devices due to their reliability and throughput. In multiprocessor system maintaining data consistency is an important parameter to be maintained because different processors communicate and share data. In multiprocessors caching plays a vital role because cache Coherence is a problem that should be handled very carefully. In this paper we have studied various Cache Coherence Protocols and simulate their behavior on various platforms on the basis of miss rate.

Key-Words / Index Term

MSI, MESI, DRAGON

References

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