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Cloud Computing is one of the most emerging field for research now a days. The cloud is responsible to provide various set of services to users which requires a lot of energy. As they are growing up with a rapid rate, the burden on cloud is increasing daily. Various researchers are working on cloud efficiency with major factor as energy efficiency. As energy efficiency will not only increase user handling rate but also decrease overall global cost and pollution. In this paper, various previous techniques used for energy efficiency are discussed on the basis various performance parameters to analyse the best available techniques.

Cloud Computing, Machine Learning, Deep Learning, Convolutional neural networks (CNN)

[1] A. Greenberg, J. Hamilton, D. A. Maltz, and P. Patel, “The cost of a cloud: research problems in data center networks,” ACM SIGCOMM computer communication review, vol. 39, no. 1, pp. 68–73, 2008.
[2] T. Heath, B. Diniz, E. V. Carrera, W. Meira Jr, and R. Bianchini, “Energy conservation in heterogeneous server clusters,” in Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming. ACM, 2005, pp. 186–195.
[3] G. Chen, W. He, J. Liu, S. Nath, L. Rigas, L. Xiao, and F. Zhao, “Energyaware server provisioning and load dispatching for connection-intensive internet services.” in NSDI, vol. 8, 2008, pp. 337–350.
[4] R. Urgaonkar, U. C. Kozat, K. Igarashi, and M. J. Neely, “Dynamic resource allocation and power management in virtualized data centers,” in Network Operations and Management Symposium (NOMS), 2010 IEEE. IEEE, 2010, pp. 479–486.
[5] A. Beloglazov and R. Buyya, “Energy efficient resource management in virtualized cloud data centers,” in Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing. IEEE Computer Society, 2010, pp. 826–831.
[6] A. Beloglazov, J. Abawajy, and R. Buyya, “Energy-aware resource allocation heuristics for efficient management of data centers for cloud computing,” Future generation computer systems, vol. 28, no. 5, pp. 755–768, 2012.
[7] A. Gandhi, Y. Chen, D. Gmach, M. Arlitt, and M. Marwah, “Minimizing data center sla violations and power consumption via hybrid resource provisioning,” in Green Computing Conference and Workshops (IGCC), 2011 International. IEEE, 2011, pp. 1–8.
[8] H. N. Van, F. D. Tran, and J.-M. Menaud, “Performance and power management for cloud infrastructures,” in Cloud Computing (CLOUD), 2010 IEEE 3rd International Conference on. IEEE, 2010, pp. 329–336.
[9] Y. C. Lee and A. Y. Zomaya, “Energy efficient utilization of resources in cloud computing systems,” The Journal of Supercomputing, vol. 60, no. 2, pp. 268–280, 2012.
[10] J. Xu and J. A. Fortes, “Multi-objective virtual machine placement in virtualized data center environments,” in Green Computing and Communications (GreenCom), 2010 IEEE/ACM Int’l Conference on & Int’l Conference on Cyber, Physical and Social Computing (CPSCom). IEEE, 2010, pp. 179–188.
[11] Z. Shen, S. Subbiah, X. Gu, and J. Wilkes, “Cloudscale: elastic resource scaling for multi-tenant cloud systems,” in Proceedings of the 2nd ACM Symposium on Cloud Computing. ACM, 2011, p. 5.
[12] B. Heller, S. Seetharaman, P. Mahadevan, Y. Yiakoumis, P. Sharma, S. Banerjee, and N. McKeown, “Elastictree: Saving energy in data center networks.” in NSDI, vol. 10, 2010, pp. 249–264.
[13] A. Berl, E. Gelenbe, M. Di Girolamo, G. Giuliani, H. De Meer, M. Q. Dang, and K. Pentikousis, “Energy-efficient cloud computing,” The computer journal, vol. 53, no. 7, pp. 1045–1051, 2010.
[14] S.-w. Liao, T.-H. Hung, D. Nguyen, C. Chou, C. Tu, and H. Zhou, “Machine learning-based prefetch optimization for data center applications,” in Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis. ACM, 2009, p. 56.
[15] P. Bodık, R. Griffith, C. Sutton, A. Fox, M. Jordan, and D. Patterson, “Statistical machine learning makes automatic control practical for internet datacenters,” in Proceedings of the 2009 conference on Hot topics in cloud computing, 2009, pp. 12–12.

Neeshu Sharma, Suresh Kumar Kaswan, "Comparative Analysis Study of Various Techniques of Energy Efficiency in Cloud Computing," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.229-234, 2019.

The DWT is expressed in a generalized form know as discrete wavelet transform which analyzes both the low and high sub bands with equal priority at every decomposition level. The DWT is a mathematical technique that provides a new method for signal processing. Due to various useful features like adaptive time-frequency window, lower aliasing distortion and efficient computational complexity, it is widely used in many signal and image processing applications. 2-D DWT is widely used in image and video compression. But flipping scheme introduces some design complexities in selected DWT structures. So in our proposed work, we have implemented BK adder and CSD technique that provides multiplier-less implementation and also will work for every bit. The proposed CSD and BK adder based 1-D and 2-D DWT algorithm shows good performance as compared to previous algorithm. The proposed architecture for DWT implementation reduces the chip area, less computation time and also minimizes the maximum combinational path delay

2-D DWT, CSD, Low-pass Sub-band (LPSB), High-pass Sub-band (HPSB), VHDL Simulation

[1] Samit Kumar Dubey, Arvind Kumar Kourav and Shilpi Sharma, “High Speed 2-D Discrete Wavelet Transform using Distributed Arithmetic and Kogge Stone Adder Technique”, International Conference on Communication and Signal Processing, April 6-8, 2017, India
[2] Maurizio Martina, Guido Masera, Massimo Ruo Roch, and Gianluca Piccinini, “Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT”, IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol .62, No.8, and August 2015.
[3] S.G. Mallat, “A Theory for Multiresolution Signal Decomposition: The Wavelet Representation”, IEEE Trans. on Pattern Analysis on Machine Intelligence, 110. July1989, pp. 674-693.
[4] M. Alam, C. A. Rahman, and G. Jullian, ”Efficient distributed arithmetic based DWT architectures for multimedia applications,” in Proc. IEEE Workshop on SoC for real-time applications, pp. 333 336, 2003.
[5] X. Cao, Q. Xie, C. Peng, Q. Wang and D. Yu, ”An efficient VLSI implementation of distributed architecture for DWT,” in Proc. IEEE Workshop on Multimedia and Signal Process., pp. 364-367, 2006.
[6] Archana Chidanandan and Magdy Bayoumi, “Area-Efficient CSD Architecture for the 1-D DCT/IDCT,” ICASSP 2006.
[7] M. Martina, and G. Masera, ”Low-complexity, efficient 9/7 wavelet filters VLSI implementation”, IEEE Trans. on Circuits and Syst. II, Express Brief vol. 53, no. 11, pp. 1289-1293, Nov. 2006.
[8] M. Martina, and G. Masera, ”Multiplierless, folded 9/7-5/3 wavelet VLSI architecture,” IEEE Trans. on Circuits and syst. II, Express Brief vol. 54, no. 9, pp. 770-774, Sep. 2007.
[9] Gaurav Tewari, Santu Sardar, K. A. Babu, ” High-Speed & Memory Efficient 2-D DWT on Xilinx Spartan3A DSP using scalable Polyphase Structure with DA for JPEG2000 Standard”, 2011 IEEE.

Anjulata Choudhary, Nishi Pandey, Meha Shrivastava, "Area and Delay Efficient 2-D DWT using Canonic Signed Digit and Brent Kung Adder Technique," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.235-239, 2019.

In a cellular network, the demand for high throughput and reliable transmission is increasing in large scale. One of the architectures proposed for 5G wireless communication to satisfy the demand is Massive MIMO system. The massive system is equipped with the large array of antennas at the Base Station (BS) serving multiple single antenna users simultaneously i.e., number of BS antennas are typically more compared to the number of users in a cell. The advantages of massive MIMO can be achieved only if Channel State Information (CSI) is known at BS uplink and downlink operate on orthogonal channels - TDD and FDD modes. Depending on slow/fast channel fading conditions, several authors suggested adaptive LMS, RLS and NLMS based channel estimators, which either require statistical information of the channel or are not efficient enough in terms of performance or computations. In order to overcome the above effects, the work focuses on the QR-RLS based channel estimation method for cell free Massive MIMO systems

Massive MIMO, Channel State Information, Square Root-Recursive Least Square (QR-RLS)

[1] Supraja Eduru and Nakkeeran Rangaswamy, “BER Analysis of Massive MIMO Systems under Correlated Rayleigh Fading Channel”, 9th ICCCNT IEEE 2018, IISC, Bengaluru, India.
[2] H. Q. Ngo A. Ashikhmin H. Yang E. G. Larsson T. L. Marzetta "Cell-free massive MIMO versus small cells" IEEE Trans. Wireless Commun. vol. 16 no. 3 pp. 1834-1850 Mar. 2017.
[3] Huang A. Burr "Compute-and-forward in cell-free massive MIMO: Great performance with low backhaul load" Proc. IEEE Int. Conf. Commun. (ICC) pp. 601-606 May 2017.
[4] H. Al-Hraishawi, G. Amarasuriya, and R. F. Schaefer, “Secure communication in underlay cognitive massive MIMO systems with pilot contamination,” in In Proc. IEEE Global Commun. Conf. (Globecom), pp. 1–7, Dec. 2017.
[5] V. D. Nguyen et al., “Enhancing PHY security of cooperative cognitive radio multicast communications,” IEEE Trans. Cognitive Communication And Networking, vol. 3, no. 4, pp. 599–613, Dec. 2017.
[6] R. Zhao, Y. Yuan, L. Fan, and Y. C. He, “Secrecy performance analysis of cognitive decode-and-forward relay networks in Nakagami-m fading channels,” IEEE Trans. Communication, vol. 65, no. 2, pp. 549–563, Feb. 2017.
[7] W. Zhu, J. and. Xu and N. Wang, “Secure massive MIMO systems with limited RF chains,” IEEE Trans. Veh. Technol., vol. 66, no. 6, pp. 5455–5460, Jun. 2017.
[8] R. Zhang, X. Cheng, and L. Yang, “Cooperation via spectrum sharing for physical layer security in device-to-device communications under laying cellular networks,” IEEE Trans. Wireless Communication, vol. 15, no. 8, pp. 5651–5663, Aug. 2016.
[9] K. Tourki and M. O. Hasna, “A collaboration incentive exploiting the primary-secondary systems cross interference for PHY security enhancement,” IEEE J. Sel. Topics Signal Process., vol. 10, no. 8, pp. 1346–1358, Dec 2016.
[10] T. Zhang et al., “Secure transmission in cognitive MIMO relaying networks with outdated channel state information,” IEEE Access, vol. 4, pp. 8212–8224, Sep. 2016.
[11] Y. Huang et al., “Secure transmission in spectrum sharing MIMO channels with generalized antenna selection over Nakagami-m channels,” IEEE Access, vol. 4, pp. 4058–4065, Jul. 2016.
[12] Y. Deng et al., “Artificial-noise aided secure transmission in large scale spectrum sharing networks,” IEEE Trans. Communication, vol. 64, no. 5, pp. 2116–2129, May 2016.

Srashti Gupta, Abhishek Bhatt, "Review paper on Massive 5G Wireless Systems with FDD and TDD Channel State Information," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.240-245, 2019.

This paper presents efficient modified distributed arithmetic (MDA)-based approaches for low delay reconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in ROM; and the ROM-based LUT is found to be costly for application specific integrated circuit (ASIC) implementation. Therefore, a shared-LUT design is proposed to realize the MDA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage

Finite Impulse Response (FIR), Look Up Table (LUT), Modified Distributive Arithmetic Technique

[1] Basant Kumar Mohanty, and Pramod Kumar Meher, High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 78, No.06, April 2016.
[2] Indranil Hatai, Indrajit Chakrabarti, and Swapna Banerjee, “An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multi-standard DUC”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 6, June 2015.
[3] Sang Yoon Park and Pramod Kumar Meher, “Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filter”, IEEE Transactions on Circuits And Systems-Ii: Express Briefs, 2014.
[4] B. K. Mohanty, P. K. Meher, S. Al-Maadeed, and A. Amira, “Memory footprint reduction for power-efficient realization of 2-D finite impulse response filters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 1, pp. 120–133, Jan. 2014.
[5] B. K. Mohanty and P. K. Meher, “A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm,” IEEE Trans. Signal Process., vol. 61, no. 4, pp. 921–932, Feb. 2013.
[6] G. Gokhale and P. D. Bahirgonde, “Design of Vedic Multiplier using Area-Efficient Carry Select Adder”, 4th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2015), Kochi, August 10-13, 2015, India.
[7] G. Gokhale and Mr. S. R. Gokhale, “Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder”, 4th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2015), Kochi, August 10-13, 2015, India.
[8] Pavan Kumar, Saiprasad Goud A, and A Radhika had published their research with the title “FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter”, 978-1-4673-6150-7/13 IEEE.
[9] B. Madhu Latha1, B. Nageswar Rao, published their research with title “Design and Implementation of High Speed 8-Bit Vedic Multiplier on FPGA” International Journal of Advanced Research in Electrical ,Electronics and Instrumentation Engineering, Vol. 3, Issue 8, August 2014.
[10] A Murali, G Vijaya Padma, T Saritha, published their research with title “An Optimized Implementation of Vedic Multiplier Using Barrel Shifter in FPGA Technology”, Journal of Innovative Engineering 2014, 2(2).
[11] Sweta Khatri, Ghanshyam Jangid, “FPGA Implementation of 64-bit fast multiplier using barrel shifter” Vol. 2 Issue VII, July 2014 ISSN: 2321-9653.
[12] Toni J. Billore, D. R. Rotake, “FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders” Journal of VLSI and Signal Processing, Volume 4, Issue 3, Ver. II (May-Jun. 2014), PP 54-59 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197.
[13] S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, “Implementation of Vedic Multiplier for Digital Signal processing” International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011.

Kriti Jain, Navneet Kaur, "Review Paper on High Performance Integrated Circuit for Multiplier-less Finite Impulse Response," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.246-250, 2019.

Programmable reversible logic circuit (RLC) is design style for nanotechnology and quantum computing with minimum heat generation, quantum cost and garbage output. Late advances in reversible rationale utilizing and quantum PC calculations consider enhanced PC engineering and math rationale unit plans. In this paper, we survey the N-bit reversible logic adder and sub tractors are used with minimal delay, and may be configured to produce a variety of logical calculations. The reversible N-bit adder/ sub tractor design is verified and its advantages over the only existing adder design are quantitatively analyzed

Reversible Gates, 4-bit Adder/ Sub tractor, Garbage Output, Quantum Cost

[1] Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azemard and Aida Todri-Sanial, “Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic”, 978-1-5386-1553-9/17/$31.00 ©2017 IEEE.
[2] Sachin Maheshwari, V.A.Bartlett and Izzet Kale, “Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers”, 978-1-5386-3974-0/17/$31.00 ©2017 IEEE.
[3] Gopi Chand Naguboina and K. Anusudha, “Design and Synthesis of Combinational Circuits Using Reversible Decoder in Xilinx”, IEEE International Conference on Computer, Communication, and Signal Processing (ICCCSP-2017).
[4] Marcin Bryk, Kryszt Gracki, Pawal Kerntop and Marek Pawlowski, “Encryption using reconfigurable reversible logic gate and its simulation in FPGAs”, Mixed Design of Integrated Circuits and Systems, 2016 MIXDES - 23rd International Conference IEEE Xplore: 04 August 2016.
[5] Umeshkumar, LavishaSahu, Uma Sharma, “Performance Evaluation of Reversible Logic Gates”, International Conference on ICT in Business Industry & Government (ICTBIG), IEEE 2016.
[6] Lafifa Jamal and Hafiz Md. HasanBabu, “Design and Implementation of a Reversible Central Processing Unit”, IEEE Computer Society Annual Symposium on VLSI, 2015.
[7] Junchaw Wing and Ken Choi, “A Carry look ahead adder designed by reversible logic”, SOC Design Conference (ISOCC), International Conference on IEEE 2015.
[8] D. Grobe, R. Wille, G.W. Dueck, and R. Drechsler, “Exact multiple control Toffoli network synthesis with sat techniques”, IEEE Transaction on CAD, 2014.
[9] Sachin Maheshwari, V.A.Bartlett and Izzet Kale, “4-phase resettable quasi-adiabatic flip-flops and sequential circuit design”, 978-1-5090-0493-5/16/$31.00 ©2016 IEEE.
[10] D.Jothi and R.Sivakumar, “A Completely Efficient Charge Recovery Adiabatic Logic Content Addressable Memory”, 2015 International Conference on Computers, Communications, and Systems.
[11] Krishna Murthy, Gayatri G, Manoj Kumar “Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate” VLSICS Vol.3, No.3, June 2012.
[12] Jayashree H V and Ashwin S, “Berger Check and Fault Tolerant Reversible Arithmetic Component Design”, 978-1- 4799 - 8364-3/ 15/ $31.00 @ 2015 IEEE.

Bhawna Yadav, Tarun Varma, "Design and Implementation of Adiabatic Sequential and Combinational circuits using Reversible Gate," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.251-255, 2019.

Now a days Internet grows up rapidly. Anything depends on network. This internet provide huge services to the users like data transfer, uploading, downloading etc… some of network services also provide security too. But here data storage is major task, its highly impossible to store huge data in network. Now the new emerging technology is cloud computing, its improve the performance, scalability and low cost to implement. Its provides many services to clients. Like upload the data retrieve the data etc… many organizations are depends on this storage service. We can install the cloud private or public or both. But cloud computing suffer from unauthorized data access. Still there is no permanent solution. These paper main objects are a) Prevent from unauthorized access b) prevent unnecessary steps to access the cloud c) To apply some tasks on cloud

cloud computing, authentication, security methods, networks, TS (Trusted System)

[1] M. Jensen, J. Schwenk, N. Gruschka, and L. Lo Iacono, On Technical Security Issues in Cloud Computing. IEEE, 2009.
[2] Greg Boss, Padma Malladi, Denis Quan, Linda Legregni, Harold Hall, “Cloud Computing”, http://www.ibm.com/developerswork/websp here/zones/hipods/library.html, October 2007, pp. 4-4
[3] “Wesam Dawoud, Ibrahim Takouna, Christoph Meinel Infrastructure as a Service Security.
[4] D. L. G. Filho and P. S. L. M. Barreto, “Demonstrating Data Possession and Uncheatable Data Transfer,” Cryptology ePrint Archive, Report 2006/150, 2006, http://eprint.iacr.org/.
[5] G. Ateniese, R. Burns, R. Curtmola, J. Herring, L. Kissner, Z. Peterson, and D. Song, “Provable Data Possession at Untrusted Stores,” Proc. of CCS ’07, pp.598–609, 2007.
[6] Arshad, J, Townsend, P. and Xu, J. (2013).A novel intrusion severity analysis approach for Clouds. Future Generation Computer Systems, 29, 416–428. doi:10.1016/j.future.2011.08.009
[7] Atayero, A.A. and Feyisetan, O. (2011). Security Issues in Cloud Computing: The Potentials of Homomorphic

Vaibhav Sardana, Nidhi Saxena, "A Novel Approach of Cloud Security by Authentication in Cloud Computing Environment," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.256-257, 2019.

In the last few years, technology, especially microprocessors, have had huge advancements and they are expected to have even more in future therefore with this rapidly growing phase of technology, is it still possible to use microprocessors that were considered to be the most advance, at the time, not to long ago? The project aims to analyse the working and applications of the AMD RYZEN microprocessor that was released in 2017. And this analysis in turn will help us to study the latest released microprocessor

Component, Formatting, Style, Styling, Insert (key words)

[1] HTTPS://WHATIS.TECHTARGET.COM/DEFINITION/RYZEN-AMD-RYZEN
[2] www.lenovo.com
[3]techradar.com/news/amd-ryzen-release-date-and featrures-everything-you-need-to-know
[4]https://www.anandtech.com/show/14947/already-working-on-2nd-gen-amds-ryzen-microsoft-surface-edition-and-what-semicustom-means
[5] amd.com/en/ryzen
[6]https://www.techradar.com/news/amd-ryzen-3000-boost-fix-works-but-its-really-not-as-big-a-deal-as-youd-think

Zaheer Maniyar, Areeba Khan, Muzammil Khan, Samad Khan, Ubaid Kolad, Mustaqim Kaderiya, "AMD RYZEN," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.258-259, 2019.

In the last few years, technology, especially microprocessors, have had huge advancements and they are expected to have even more in future therefore with this rapidly growing phase of technology, is it still possible to use microprocessors that were considered to be the most advance, at the time, not to long ago? The project aims to analyze the working and applications of the pentium 4 microprocessor that was released in November 20,2000. And this analysis in turn will provides an in-depth examination of the features and function of Pentium 4 microprocessor

Component, Formatting, Style, Styling, Insert (key words)

[1] WWW.ECS.UMASS.EDU {RESEARCH PAPER FOR PENTIUM 4 MICR0 PROCESSOR}
[2] D.SAGAR, G.HINTON, M.UPTON, T.CHAPPERLL, T.FLETCHER, S.SAMAAN AND R.MURRAY,
[3] THE UNABRIDGED PENTIUM 4:IA32 PROCESSORGENEALOGY (PC SYSTEM ARCHITECTURE)
[4] techreport.com/review/5292/intels-pentium

Sayed Heena, Salman Shaikh, Taha shaikh, Abdul Rashid, Nadim Khatri, "Pentium 4: Old School yet Modern in Engineering," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.260-261, 2019.

Since the computer is invented the main heart of the computer is the CPU (performance). We have researched from the earlier paper that processor was not enough to compute with the performance. This paper, explains the characteristics of processor performance and its implementation for several configurations, Including Intel quad core processor, Quad-core multi-processor, Quad Core CPU Chip having 4 cores on one single chip, Thread-Level Parallelism. Using the clock rate, the CPU’s execution time, which is the total time the processor takes to process some program in seconds per program (total number of bytes), can be calculated. We propose a performance evaluation methodology affected by a benchmark test. Measuring of such systems performance becomes an important task for any system embedded design process

CPU performance, throughput, speed

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[3] V.P. RAMAMURTHI ; K.A.M. JUNAID ; S. SARAVANAN, “DESIGN OF FIRING SCHEME USING 8085 MICROPROCESSOR FOR VARIABLE FREQUENCY THREE PHASE AC POWER CONTROLLER”, ”,IEEE CONFRENCE, NEW DELHI, INDIA, INDIA, 28-30 AUG. (1991)
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[7] Abhishek Yadav, “Microprocessor 8085, 8086”
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[10]S.K. Sen “Understanding 8085/8086 Microprocessors and Peripheral ICs Through Questions and Answers” Edited by New Age International Publishers (2010), pp.1-303.
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Abuzar Shaikh, Gokul Nair, Arshad Pathan, Ashish Panda, Shakila Shaikh, Shiburaj Pappu, "Processor Performance," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.262-264, 2019.

Crime, an unlawful act, causes terror and threat to our society and is a major concern for national security. However, very negligible work has been done to develop models and methods to hold an active collaboration between forensic science and criminal investigation systems. The need is felt to develop a system that collects as well as categorise the data on crimes along with an analysis of crime affected areas identification. In this study, an efficient crime investigation system is proposed in which fuzzy rules and Regression clustering algorithm is employed to identify and detect crime affected region along with showing it on the map. The study of DATA GATHERING is incorporated for crime detection and prevention with an aim to provide a safer society to live

Crime detection, cloud computing, data mining, clustering, Internet of things

[1] Q.Rossy, O.Ribaux, “ A collaborative approach for incorporating forensic data into crime investigation using criminal intelligence analysis and visualisation” Forensic Science and Justice, Vol. 54 , 2014 , pp. 146-153.
[2] Q.Rossy, S.Ioset, D. Dessimoz, and O. Ribaux, “Integrating forensic information in a crime intelligence database,” Forensic Sci. Int., vol. 230, no. 1–3, pp. 137–146, 2013.
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[8] G. Oatley, “Crimes analysis software : ‘ Pins in Maps ’, clustering and Bayes net prediction, ” Expert Systems with Applications , vol. 25, no. March, pp. 569–588, 2016.
[9] T. H. Grubesic, “On the application of fuzzy clustering for crime hot spot detection,” J. Quant. Criminol., vol. 22, no. 1, pp. 77–105, 2006.
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[11] K. Stoffel, P. Cotofrei, and D. Han, “Fuzzy Clustering based Methodology for Multidimensional Data Analysis in Computational Forensic Domain,” Itcf 2010, vol. 4, pp. 400–410, 2011.
[12] A. Juyal, O. Gupta, “A review on clustering techniques”, International Journal of Advanced Research in Computer Science and Software Engineering, Vol. 4, 2014.
[13] T.Moon, S.Heo, S.Lee, “Ubiquitous crime prevention system for a safer city”, Environmental Sciences, Vol. 22, pp. 288-301,2014.
[14] S. K. Sood, “Dynamic Resource Provisioning in Cloud based on Queuing Model,” vol. 2, no. 4, 2013.
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Minakshi Pathania, Isha Awasthi, "Detection of Crime Using the Application of Regression Mechanism," International Journal of Computer Sciences and Engineering, Vol.7, Issue.10, pp.265-272, 2019.