Network on Chip (NoC) is an interconnection network, which provides a network architecture to overcome limitations of System on Chip(SoC). The Interconnection among multiple cores on a chip has a major effect on communication and performance of the chip in terms of latency and throughput. Many routing architectures and routing algorithm have been developed to alleviate traffic congestion, performance enhancement and low power consumption for Network on Chip(N0C). In this paper, Diagonal Mesh NoC architecture is described using Network Simulator (NS2), which reduces the load distribution across the network by reducing the diameter of the network, as a result, routing cost also reduces. In Diagonal Mesh topology, routing estimates the alternative routes with priority given to a diagonal path. In this paper, it is seen that latency reduces for a pair of nodes that uses the diagonal path as compared to another pair of nodes. Throughput is also enhanced by this approach.

Network on Chip (NoC), Topology, Latency, Throughput, NS2

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